Complimentary metal oxide semiconductor (CMOS) image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells. Each one of the cells includes a photo-conversion device, such as a photogate, photoconductor, or photodiode, overlying a charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, and a transistor, for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of photo-generated charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state before a transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node. Photo-generated charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the sensing node is typically converted to a pixel output voltage by a source follower output transistor.
CMOS image sensors of the type discussed above are generally known and are discussed in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe operation of conventional CMOS image sensors, the contents of which are incorporated herein by reference.
A schematic top view of a portion of a semiconductor wafer fragment containing a conventional CMOS pixel cell is shown in FIG. 1. The CMOS pixel cell 10 is a four transistor (4T) cell. The pixel cell 10 generally comprises a photo-conversion device 21 for collecting charges generated by light incident on the pixel, and a transfer gate 7 for transferring photoelectric charges from the photo-conversion device 21 to a sensing node 4, typically a floating diffusion region 4. The floating diffusion region 4 is electrically connected to the gate of an output source follower transistor 11. The pixel cell 10 also includes a reset transistor 9 for resetting the floating diffusion region 4 to a predetermined voltage before a photoelectric charges are transferred; a source follower transistor 11 which receives at its gate an electrical signal representative of the photoelectric charges from the floating diffusion region 4; and a row select transistor 13 for outputting a signal from the source follower transistor 11 to an output terminal in response to an address signal.
FIG. 2 is a diagrammatic side sectional view of the pixel cell 10 of FIG. 1 taken along line 2-2′. As shown in FIG. 2, in the conventional CMOS pixel cell 10 the photo-conversion device 21 is a pinned photodiode. The pinned photodiode 21 has a photosensitive p-n-p junction region comprising a p-type surface layer 5 and an n-type photodiode region 14 within a p-type active layer 1, which is typically a lightly doped p-active area. Adjacent to the pinned photodiode 21 is a gate 7 of a transfer transistor. Typically, the transfer gate 7 is an n+ gate having a gate electrode 8 comprising a layer of heavily doped n-type polysilicon.
In the conventional CMOS pixel cell 10 depicted in FIGS. 1 and 2, charge in the form of electrons is generated by light incident externally to the pixel cell 10 and stored in the n-type photodiode region 14. This charge is transferred to the floating diffusion region 4 by the gate 7 of the transfer transistor. The source follower transistor 11 produces an output signal from the transferred charges. The output signal is proportional to the charge, or number of electrons, extracted from the n-type photodiode region 14.
Optimizing the characteristics of a transfer gate device is critical to providing a high performance CMOS image sensor. Ideally, a transfer gate should have very low leakage in the off state, a low threshold voltage, and no potential barriers that impede the flow of electrons in a region 30 where a photo-conversion device, such as the pinned photodiode 21, and transfer gate are in close proximity to one another. These characteristics can often conflict with one another and optimizing them is difficult.
In a conventional CMOS pixel cell having a photo-conversion device, such as pinned photodiode 21, a potential barrier might exist where the transfer gate 7 and pinned photodiode 21 are in close proximity: the photodiode/transfer gate region 30. FIG. 3 is a graph representing the potential (V) in the pixel cell 10 along the distance (D) of line 3-3′ (FIG. 2) in a direction from the pinned photodiode 21 to the transfer gate 7 and the floating diffusion region 4 of the CMOS pixel cell 10. The potential profile of FIG. 3 shows the potentials that an electron may encounter, including a potential barrier 31, as it is transferred from the pinned photodiode 21 to the floating diffusion region 4.
As shown in FIG. 3, there is a potential barrier 31 corresponding to the photodiode/transfer gate region 30. If this potential barrier is too high, a portion of the charge will be unable to move from the photodiode 21 to the floating diffusion region 4. The greater the potential barrier, the less charge will be transferred to the floating diffusion region 4. This potential barrier is influenced by the characteristics of the pixel cell 10, including: 1) p-type dopant levels in the channel region of the transfer gate 7; 2) dopant levels in the transfer gate 7 channel region used to adjust the threshold voltage; 3) transfer gate 7 oxide thickness; 4) pinned photodiode 21 surface p-type dopant levels; 5) pinned photodiode 21 n-type dopant levels; and 6) any background p-type dopant concentration.
The existence of a potential barrier in the photodiode/transfer gate region 30 is a significant problem in CMOS image sensors. A potential barrier in the photodiode/transfer gate region 30 causes incomplete charge transfer reducing the charge transfer efficiency of the pixel cell 10. Further, charge remaining in the photodiode 21 can affect charge collected for a subsequent image causing image lag, where a ghost image from the initial charge is apparent in a subsequent image. Previous methods to reduce this potential barrier have resulted in degraded sub-threshold leakage current for the transfer gate 7. It is difficult to optimize both the potential barrier and sub-threshold leakage current for the transfer gate 7 in CMOS image sensors. Accordingly, what is desired is a technique for manufacturing a CMOS pixel cell having both a reduced potential barrier in an area where a photodiode and a transfer gate structure are in close proximity to one another and also with low sub-threshold leakage characteristics.